1 industrial temperature range idt74alvc125 3.3v cmos quadruple bus buffer gate september 2000 1999 integrated device technology, inc. dsc-4635/- c idt74alvc125 industrial temperature range 3.3v cmos quadruple bus buffer gate with 3-state outputs applications: ? 3.3v high speed systems ? 3.3v and lower voltage computing systems functional block diagram drive features for alvc125: C high output drivers: 24ma C suitable for heavy loads description: this quadruple bus buffer gate is built using advanced dual metal cmos technology. the alvc125 features independent line drivers with 3-state outputs. each output is disabled when the associated output-enable ( oe ) input is high. the alvc125 has been designed with a 24ma output driver. this driver is capable of driving a moderate to heavy load while maintaining speed performance. 1 a 1 oe 1 2 1 y 3 2 a 2 oe 4 5 2 y 6 3 a 3 oe 10 9 3 y 8 4 a 4 oe 13 12 4 y 11 features: C 0.5 micron cmos technology C esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) Cv cc = 3.3v 0.3v, normal range Cv cc = 2.7v to 3.6v, extended range Cv cc = 2.5v 0.2v C cmos power levels (0.4 w typ. static) C rail-to-rail output swing for increased noise margin C available in soic, ssop and tssop packages
2 industrial temperature range idt74alvc125 3.3v cmos quadruple bus buffer gate symbol description max. unit v term (2) terminal voltage with respect to gnd C 0.5 to + 4.6 v v term (3) terminal voltage with respect to gnd C 0.5 to v cc + 0.5 v t stg storage temperature C 65 to + 150 c i out dc output current C 50 to + 50 ma i ik continuous clamp current, v i < 0 or v i > v cc 50 ma i ok continuous clamp current, v o < 0 C 50 ma i cc i ss continuous current through each v cc or gnd 100 ma alvc quad link absolute maximum ratings (1) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 5 7 pf c out output capacitance v out = 0v 7 9 pf c i/o i/o port capacitance v in = 0v 7 9 pf alvc quad link note: 1. as applicable to the device type. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v cc terminals. 3. all terminals except v cc . pin description pin configuration 2 3 14 1 1 oe v cc 5 6 4 gnd 7 13 12 10 9 11 8 1 a 1 y 2 oe 2 a 2 y 4 oe 4 a 4 y 3 oe 3 a 3 y so14-1 so14-2 so14-3 soic/ ssop/ tssop top view pin names description x oe output enable inputs (active low) xa data inputs xy 3-state outputs capacitance (ta = +25c, f = 1.0mhz) function table (each buffer) (1) note: 1. h = high voltage level l = low voltage level x = don't care z = high-impedance inputs output xoe xa xy lh h ll l hx z
3 industrial temperature range idt74alvc125 3.3v cmos quadruple bus buffer gate c output drive characteristics symbol parameter test conditions (1) min. max. unit v oh output high voltage v cc = 2.3v to 3.6v i oh = C 0.1ma v cc C 0.2 v v cc = 2.3v i oh = C 6ma 2 v cc = 2.3v i oh = C 12ma 1.7 v cc = 2.7v 2.2 v cc = 3.0v 2.4 v cc = 3.0v i oh = C 24ma 2 v ol output low voltage v cc = 2.3v to 3.6v i ol = 0.1ma 0.2 v v cc = 2.3v i ol = 6ma 0.4 i ol = 12ma 0.7 v cc = 2.7v i ol = 12ma 0.4 v cc = 3.0v i ol = 24ma 0.55 alvc quad link note: 1. v ih and v il must be within the min. or max. range shown in the dc electrical characteristics over operating range table for the appropriate v cc range. t a = C 40c to + 85c. dc electrical characteristics over operating range following conditions apply unless otherwise specified: operating condition: t a = - 40 c to +85 c symbol parameter test conditions min. typ. (1) max. unit v ih input high voltage level v cc = 2.3v to 2.7v 1.7 v v cc = 2.7v to 3.6v 2 v il input low voltage level v cc = 2.3v to 2.7v 0.7 v v cc = 2.7v to 3.6v 0.8 i ih input high current v cc = 3.6v v i = v cc 5a i il input low current v cc = 3.6v v i = gnd 5 i ozh high impedance output current v cc = 3.6v v o = v cc 10a i ozl (3-state output pins) v o = gnd 10 a v ik clamp diode voltage v cc = 2.3v, i in = C 18ma C 0.7 C 1.2 v v h input hysteresis v cc = 3.3v 100 mv i ccl i cch quiescent power supply current v cc = 3.6v v in = gnd or v cc 0.110a d i cc quiescent power supply current variation one input at v cc - 0.6v, other inputs at v cc or gnd 750 a note: 1. typical values are at v cc = 3.3v, +25c ambient.
4 industrial temperature range idt74alvc125 3.3v cmos quadruple bus buffer gate operating characteristics, t a = 25 o c switching characteristics (1) note: 1. see test circuits and waveforms. t a = C 40c to + 85c. v cc = 2.5v 0.2v v cc = 3.3v 0.3v symbol parameter test conditions typical typical unit c pd power dissipation capacitance per gate outputs enabled c l = 0pf, f = 10mhz 20 30 pf c pd power dissipation capacitance per gate outputs disabled 3 6 pf v cc = 2.5v 0.2v v cc = 2.7v v cc = 3.3v 0.3v symbol parameter min. max. min. max. min. max. unit t plh t phl propagation delay xa to xy 13.113.11.13ns t pzh t pzl output enable time x oe to xy 1.5 5.4 1.5 5.3 1.5 4.5 ns t phz t plz output disable time x oe to xy 1 4.1 1.3 4.4 1.7 4.2 ns
5 industrial temperature range idt74alvc125 3.3v cmos quadruple bus buffer gate open v load gnd v cc pulse generator d.u.t. 500 w 500 w c l r t v in v out (1, 2) alvc link input v ih 0v v oh v ol t plh1 t sk (x) output 1 output 2 t phl1 t sk (x) t plh2 t phl2 v t v t v oh v t v ol t sk (x) = t plh2 - t plh1 or t phl2 - t phl1 alvc link same phase input transition opposite phase input transition 0v 0v v oh v ol t plh t phl t phl t plh output v ih v t v t v ih v t alvc link data input 0v 0v 0v 0v t rem timing input synchronous control t su t h t su t h v ih v t v ih v t v ih v t v ih v t alvc link asynchronous control low-high-low pulse high-low-high pulse v t t w v t alvc link control input t plz 0v output normally low t pzh 0v switch closed output normally high enable disable switch open t phz 0v v lz v oh v t v t t pzl v load/2 v load/2 v ih v t v ol v hz alvc link test cir cuits and w a veforms test conditions propagation delay test circuits for all outputs enable and disable times set-up, hold, and release times switch position output skew - tsk (x) definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. note: 1. diagram shown for input control enable-low and input control disable-high. notes: 1. pulse generator for all pulses: rate 10mhz; t f 2.5ns; t r 2.5ns. 2. pulse generator for all pulses: rate 10mhz; t f 2ns; t r 2ns. pulse width symbol v cc (1) = 3.3v 0.3v v cc (1) = 2.7v v cc (2) = 2.5v 0.2v unit v load 662 x vccv v ih 2.7 2.7 vcc v v t 1.5 1.5 vcc / 2 v v lz 300 300 150 mv v hz 300 300 150 mv c l 50 50 30 pf alvc quad link test switch open drain disable low enable low v load disable high enable high gnd all other tests open alvc quad link notes: 1. for t sk (o) output1 and output2 are any two outputs. 2. for t sk (b) output1 and output2 are in the same bank.
6 industrial temperature range idt74alvc125 3.3v cmos quadruple bus buffer gate *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. the idt logo is a registered trademark of integrated device technology, inc. ordering information corporate headquarters for sales: 2975 stender way 800-345-7015 or 408-727-6116 santa clara, ca 95054 fax: 408-492-8674 www.idt.com* idt xx alvc xxx xx package device type temp. range 74 quadruple bus buffer gate with 3-state outputs, 24ma C 40c to +85c 125 dc py pg small outline ic (so14-1) shrink small outline package (so14-2) thin shrink small outline package (so14-3)
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